d-Matrix

Market leader in data center AI acceleration, offering Blackwell and Hopper GPU architectures with complete software stack maturity (CUDA, cuDNN, TensorRT) and NVLink interconnects for massive LLM training and high-throughput inference.

Direct high-performance competitor in data center AI hardware, delivering CDNA 3-based Instinct accelerators with leading HBM3/HBM3E memory capacities and the open-source ROCm software stack for hyperscale training and inference clusters.

Provides dedicated deep learning accelerators engineered for generative AI training and inference at scale, featuring native integrated RDMA-over-Converged-Ethernet (RoCE) networking to lower cluster interconnect TCO.

Engineers wafer-scale engine supercomputing systems designed specifically for large language model pre-training and ultra-fast real-time inference without traditional multi-chip distributed communication bottlenecks.

Develops reconfigurable dataflow unit (RDU) accelerators tailored for continuous inference and training, utilizing memory tiering across SRAM, HBM, and DDR for complex agentic and frontier AI models.

Pioneers Language Processing Units (LPUs) utilizing deterministic tensor streaming architectures and massive on-chip SRAM for ultra-low latency, high-throughput LLM token generation.

Produces open, RISC-V and Tensix core-based AI graph processors and dense rack-scale servers designed for scale-out neural network training and high-throughput inference with an open-source compiler toolchain.

Offers high-density, low-power PCIe inference accelerator cards and data center appliances engineered to maximize compute density and power efficiency for enterprise NLP and generative AI workloads.

Builds dedicated data center NPU accelerators featuring UCIe chiplet interconnects and HBM, optimizing large-scale transformer inference throughput and total cost of ownership against mainstream server GPUs.